1. Field of the Invention
This invention relates generally to a method and apparatus for testing semiconductor chip devices and, more particularly, to AC time delay fault testing (AC path delay) of high speed semiconductor chip common input/output (I/O), also known as bidirectional I/O (BIDI).
2. Discussion of the Related Art
In the testing of semiconductor chip devices, such as application specific integrated circuit (ASIC) and/or microprocessors with high speed I/O's, time intervals for particular semiconductor chip functions, such as access, setup, and hold times, are desired to be measured. With current known semiconductor chip testing technology, time intervals are measured by a tester external to the semiconductor chip, wherein the tester provides appropriate testing signals and measures corresponding response times for a particular tested function. The particular semiconductor chip device is then characterized and classified based upon the measured response time. Furthermore, in view of very small time intervals, on the order of less than one nanosecond (&lt;1 ns), and higher semiconductor device operating speeds or rates, on the order of greater than 200 MHZ, testing of semiconductor chip devices is becoming increasingly difficult to do with a high degree of accuracy.
Testing of input/output ports (I/O's) of semiconductor chips has historically been performed with a physical tester/DUT (device under test) interface and an appropriate set of test signal patterns, waveforms, and timings created by a tester in accordance with a particular semiconductor device or chip testing procedure. As semiconductor device speeds increase, however, the accuracy of the present known types of measurements greatly diminish due to the dynamics of the interface between the tester and the device under test. Mismatched transmission lines, poor or no terminations on signal line leads, cross talk between adjacent signal lines, noise, inductance of particular fixturing of the tester/DUT interface, high pin (or pad) counts, high delta I's (i.e., changes in power line currents per unit time), and many other causes contribute to making the tester/DUT interface and fixturing errors a prominent portion of any measurement done in the greater than approximately 250 MHZ range. In other words, testing integrity of the tester/DUT interface and fixturing, for measurements done in the greater than 250 MHZ range, suffer adversely due to undesirable affects involved in the dynamics of the interface between the tester and the DUT during a testing procedure.
Errors in measurements include tester driver skew, tester measurement error, and fixturing errors, incurred when an output impedance Z.sub.out of the DUT driver has an impedance of anything but that of the tester, typically 50 ohms. This could be as large as multiples of a round trip fixture time (typically on the order of 2.5 ns (nanoseconds)) when there are large impedance mismatches (on the order of greater than fifty percent (&gt;50%)) between the DUT driver impedance and the tester fixturing impedance, further wherein the test signal cannot be terminated at the tester end. Tester driver skew refers to a deviation from a true value or ideal tester driver signal. Typical tester driver skew is on the order of 125-300 ps (picoseconds).
In one instance, I/O's of a semiconductor chip designed to drive low picofarad (i.e., on the order of 2 to 5 pf) wirebond or daughtercard traces to static random access memory (SRAM) devices are in fact loaded with 50 ohm AC (alternating current) loads to ground (i.e., ground potential). Such loading to AC ground due to the characteristics of transmission lines, which may occur, for example, for a period of time on the order of 3 to 5 ns (corresponding to a round trip time for the tester fixturing), severely degrades the actual performance of the semiconductor chip I/O's drivers. As a result of the degraded testing performance, the device under test may end up being characterized as a slower part, when in reality, it is a faster part. In other words, the faster part ended up being mis-classified as a slower part due to testing errors. Furthermore, it is not desirable for faster parts to be mis-binned as slower parts.
I/O mismatch is a large factor in an error budget for semiconductor chip testing. Typical tester measurement error in on the order of 225-425 Ps. Furthermore, mismatch error is a function of the actual DUT impedance, which further varies from chip to chip, driver to driver. As a result, undesired nanosecond errors can be easily created using test apparatus known in the art.
Testing of large complex logic circuits by scan test methodologies includes the use of test patterns or vectors being shifted into shift register latches, such as disclosed in U.S. Pat. No. 5,544,173, assigned to the assignee of the present invention and incorporated herein by reference. The shift register latches are typically components of functional registers in the logic circuit. Testing of large complex circuits to detect AC or delay faults includes shifting into a particular shift register latch a pattern of a logic "0" followed by a logic "1" or vice versa in such a manner as to cause a transition of the observable output of a logic circuit under test. For example, one scan test methodology, such as Level Sensitive Scan Design (LSSD), has been extended to the testing for AC delay faults. AC delay faults correspond to those circuit faults wherein the circuits behave correctly according to the static logical equations expected, however, the circuits do not assume these values in the correct time but take longer than expected to assume the correct value. Using scan techniques to detect AC delay faults requires a time sequence of first and second test vectors. The first test vector sensitizes the logic path to be tested. The second test vector provides the appropriate plurality of logical "0" to "1" and "1" to "0" transitions from the first test vector to cause an observable logical output to switch. This output can be captured into a shift-register latch with an appropriate clock. If the correct value is captured, it is seen that the sensitized path switched with no more delay than the time between the presentation of the second test vector and the capture clock.
In prior known methods of doing an AC performance test of an output I/O, a test set-up would include a tester having a driver, driver fixturing to the device under test, receiver fixturing from the device under test, and a tester receiver. To test an output I/O would include launching a transition from the tester driver, go through fixturing, go through a DUT receiver, go through chip logic, whether it be a clock fan out logic or other mechanism, and induce the DUT driver to make a transition. Once the DUT driver has been induced with the transition, the induced transition then has to travel across the fixturing and be captured by the tester receiver. In the known method, both the launching mechanism and its associated clock, and the receiving mechanism and its associated clock are in the tester. There are two problems associated in that situation, one being larger than the other. The fixturing error is essentially a mismatch in impedance between the device under test driver and the tester fixturing. Generally, the tester fixture impedance is fixed, thus, depending upon how large the mismatch is, there is ringing and overshoot which may predominate in the AC delay fault measurement of the DUT driver, which disadvantageously causes errors in the measurement. In the presence of such errors, it is possible to characterize (based upon faulty testing by the tester) a very low impedance, fast chip slow. For various reasons, it's not always, or seldom possible to accurately match the output impedance of the device driver under test and the tester. There exists sufficient variation in process technology that if you intended to match impedances, the impedances would not match to within five or ten percent (i.e., where process technology refers to the particular technology used in the manufacture of the particular chip, such as, 0.25 .mu.m technology).
It would thus be desirable to provide a method and apparatus for providing an optimal testing of AC fault delays of very complex semiconductor device logic circuits which does not suffer from the problems as discussed herein above.